1. Field of the Disclosure
The present disclosure generally relates to the fabrication of integrated circuits that include multi-layer dielectric stacks that contain one or more low-k dielectric layers.
2. Description of the Related Art
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the substrate. Efficient routing of these signals across the device requires formation of multi-level or multi-layered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper (Cu), since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum (Al) based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of interfering signals in adjacent metal lines (known as “cross-talk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant (k) of less than 3.0 (low-k). More recently low-k dielectrics comprising organosilicon layers have been developed with k values less than about 3.0, and even less than about 2.5.
One method that has been used to develop low-k organosilicon layers has been to deposit the layers from a gas mixture comprising one or more organosilicon compounds and one or more organic porogen compounds. Herein, an organosilicon matrix is produced in which the porogen molecule is trapped. The porogen molecule is thermally labile and may contain volatile chemical groups. Thermal and/or ultraviolet (UV) radiation may be subsequently used to remove the porogens and/or volatile groups from the deposited layers to create nanometer-sized pores or voids in the layers. The presence of pores or voids lowers the dielectric constant of the layers, as air has a dielectric constant of approximately 1.
However, the porous low-k layers described above may be susceptible to damage during subsequent semiconductor processing steps that involve energetic plasma. One result of plasma damage is an increase in the dielectric constant of the dielectric layers, which in turn can increase parasitic capacitance and cross-talk between adjacent copper lines. An example of a damaging plasma processing step involves the deposition of a barrier layer, such as a cobalt metal cap or dielectric layer over or upon the copper lines, which may be used to prevent the electromigration (EM) of copper from adjacent copper lines. Electromigration may cause short circuits between lines, as well as void formation within a line or at an interface, which may lead to an open circuit.
Electromigration is one of the main reliability concerns for very large scale integrated (VLSI) circuits and manufacturing, and plasma deposition of barrier layers is typically used to help prevent EM in copper lines in most devices today. Therefore, there is a need for a method of forming one or more low-k layers and then protecting the formed low-k layers from plasma damage during the barrier layer deposition process, and thereby maintain the overall dielectric constant of the multi-layer dielectric stack or structure.